Raspberry Pi Pico 2

Just as good, but better

With a higher core clock speed, double the memory, more powerful Arm cores, optional RISC‑V cores, new security features, and upgraded interfacing capabilities, Raspberry Pi Pico 2 delivers a significant performance boost, while retaining compatibility with earlier members of the Raspberry Pi Pico series.

Programmable in C / C++ and Python, and with detailed documentation, Raspberry Pi Pico 2 is the ideal microcontroller board for enthusiasts and professional developers alike.

Raspberry Pi RP2350 specifications:

• CPU
  • Dual-core Arm Cortex-M33 @ 150 MHz with Arm Trustzone, Secure boot
  • Dual-core 32-bit RISC-V Hazard3 @ 150 MHz (3-stage in-order pipeline; RV32IMAC with Zba, Zbb, Zbs, Zbkb, Zcb, Zcmp, and Zicsr extensions)
  • Up to two cores can be used at a time, either 2x Arm, 2x RISC-V, or 1x Arm + 1x RISC-V
• Memory – 520 KB on-chip SRAM
• Storage – Up to 16MB external QSPI flash
• Peripherals
  • RP2350A: up to 30x GPIOs, up to 4x ADC, up to 16x PWM channels
  • RP2350B: up to 48x GPIOs, up to 8x ADC, up to 24x PWM channels
  • USB 1.1 host/device
  • 2x UART
  • 2x SPI controllers
  • 2x I2C controllers
  • 3x PIO blocks, 12x PIO (Programmable IO) state machines
  • HSTX (high-speed serial transmit) streams data from the system clock domain to up to 8 GPIOs (IO12-IO19) at a rate independent of the system clock.
  • Temperature sensor
• Security
  • 8KB of anti-fuse OTP for key storage
  • SHA-256 acceleration
  • Hardware TRNG
  • Fast glitch detectors
• Debugging – SWD Debug interface
• Low power – Extended low-power sleep states with optional SRAM retention: as low as 10 μA DVDD
• Package
  • RP2350A – QFN-60; 7×7 mm
  • RP2350B – QFN-80; 10×10 mm

As I understand it, the RP2350A package offers also the same pinout as the RP2040 microcontroller, but the company now also adding a larger RP2350B package with additional GPIOs and analog inputs.

Raspberry Pi used the same method as for the RP2040 to derive the RP2350 name. RP stands for “Raspberry Pi”, “2” is the number of cores, “3” refers to the MCU core used (e.g. Cortex-M33), and the last two numbers “4” and “0” use floor(log2(x/16k)) formula to calculate a number representing the SRAM and non-volatile storage capacity inside the chip.

I can see some reference to RP235x online, so we may see an RP2354 or similar in the future with embedded flash. [Update: RP2354A and RP2354B packages will be sold with 2MB flash]

Arm/RISC-V switching is explained as follows in the datasheet:

RP2350 supports both Arm and RISC-V processor architectures. SDK-based programs which do not contain assembly code typically run unmodified on either architecture by providing the appropriate build flag.

There are two processor sockets on RP2350, referred to as core 0 and core 1 throughout this document. Each socket can be occupied either by a Cortex-M33 processor (implementing the Armv8-M Main architecture, plus extensions) or by a Hazard3 processor (implementing the RV32IMAC architecture, plus extensions).

When a processor reset is removed, hardware samples the ARCHSEL register in the OTP control register block to determine which processor to connect to that socket. The unused processor is held in reset indefinitely, with its clock inputs gated. The default and allowable values of the ARCHSEL register are determined by critical OTP flags:

1. If CRIT0_ARM_DISABLE is set, only RISC-V is allowed.
2. Else if CRIT0_RISCV_DISABLE is set, only Arm is allowed.
3. Else if CRIT1_SECURE_BOOT_ENABLE is set, only Arm is allowed.
4. Else if CRIT1_BOOT_ARCH is set, both architectures are permitted, and the default is RISC-V.
5. If none of the above flags are set, both architectures are permitted, and the default is Arm.

The presence of RISC-V cores is probably as a first try for experimentation, and future Raspberry Pi microcontrollers may end up being RISC-V only. Let’s wait and see.

Raspberry Pi Pico 2 specifications

• SoC – Raspberry Pi RP2350
  • CPU
    • Dual-core Arm Cortex-M33 @ 150 MHz with Arm Trustzone, Secure boot OR
    • Dual-core RISC-V Hazard3 @ 150 MHz
  • Memory – 520 KB on-chip SRAM
  • Security
    • 8KB of anti-fuse OTP for key storage
    • Secure boot (Arm only)
    • SHA-256 acceleration
    • Hardware TRNG
    • Fast glitch detectors.
  • Package – QFN-60
• Storage – 4 MB on-board QSPI flash
• USB – Micro USB 1.1 host/device connector for power and programming
• Expansion – 26-pin GPIO header with
  • 2x UART
  • 2x SPI controllers
  • 2x I2C controllers
  • 16x PWM channels
  • 4x ADC
  • 3x PIO blocks, 12x PIO (Programmable IO) state machines
• Debugging – SWD debug interface
• Power Supply – 1.8 to 5.5V DC
• Dimensions – 51 x 21 mm
• Temperature Range – -20°C to +85°C

My Raspberry Pi Pico 2 should be delivered by DHL today or tomorrow, so I haven’t been able to play with it yet, but as I understand it, it will use the same C/C++ and Python SDK as for the Raspberry Pi Pico/RP2040 plus extra features for the security, and a new toolchain for the RISC-V if you’re going to use it. More details should now be available on the documentation website, as well as on GitHub with the Pico SDK and examples.

Third-party RP2350 boards will launch at the same time as the Raspberry Pi Pico 2 board, and I already have a Cytron MOTION 2350 PRO board for robot control with an RP2350A microcontroller on my desk…

Chip off the new block

Raspberry Pi Pico 2 is powered by RP2350, our new high-performance, secure microcontroller. Every aspect of the design has been upgraded, from the CPU cores to our unique PIO interfacing subsystem. We’ve introduced a comprehensive security architecture, built around Arm TrustZone for Cortex-M. And new low-power states and package options expand the range of addressable applications.